1. Field of Art
The disclosure generally relates to the field of electronic design automation (EDA), and more specifically to methods and apparatuses for automatic legalization of an integrated circuit layout on non-uniform grids.
2. Description of the Related Art
Advancements in process technology have impacted integrated circuit manufacturing in at least two key ways. Firstly, scaling of device geometry achieved through sub-wavelength lithography has facilitated the packing of more devices on a chip. Secondly, different fabrication process recipes have enabled the manufacturing of heterogeneous devices with different threshold and supply voltages on the same die. A consequence of these improvements, however, has been an explosion in the number of design rules that need to be obeyed in the layout. Instead of simple width and spacing rules, modern fabrication technologies prescribe complex contextual rules that have to be obeyed for manufacturability. The increase in the number of rules has complicated the task of creating design rule clean layouts, i.e., layouts that do not have design rule violations. Creating design rule clean layouts for digital circuit designs can be facilitated by the use of standard cell layouts as building blocks, and placement and routing tools that are extended to address the design rules.
Unfortunately, this approach may not be applicable to analog, mixed signal and RF circuit designs. Layouts for such designs are typically created manually using layout editors, and, because of the number and complexity of the design rules, checking and fixing (i.e., legalizing) them can become a laborious process.
Advanced processes (22 nanometers (nm) and below) bring new challenges to layout designs. These advanced processes employ restrictive design rules (RDR) where all shapes in some layers (especially polysilicon) have the same orientation, the same width, and the same pitch. To define where layout objects can be placed in a layer, grids can be specified for each layer in the layout. The grids could be specified in a horizontal, a vertical or both directions to define positional values. Unlike a single manufacturing grid in older processes, these RDRs impose layer specific grids. Thus, layouts now need to obey multiple grid constraints. Furthermore, the grids need not be uniform for a layer, but rather different grid pitches could be defined for the same layer at different locations in the design. The non-uniformity of the grids may arise out of design methodologies. For such layers, in addition to uniform grids, centerlines of rectangular portions of layout shapes may need to be incident on non-uniform grids (i.e., tracks). Similarly, via centers may need to be located at the intersection of the tracks of their corresponding bottom and top layers.
Therefore, there is a need for an improved concept providing a robust solution to the problem of layout editing, in a manner that avoids and fixes non-uniform grid constraints with a minimal perturbation from the original form.